Physical Design Stages

1. Data Preparation

2. Sanity Checks

3. Floor planning

4. Power planning

5. Placement

6. PreCTS Optimization

7. Clock Tree Synthesis

8. PostCTS Optimization

9. Routing

10. PostRoute Optimization

11. Via Optimization

12. Metal Fill

13. QRC extraction

14. Crosstalk Analysis

15. ETS

16. Physical Verification(DRC and LVS)

17. IR-Drop Analysis

Sub domains in VLSI

Under VLSI following areas are there :

1. Verification

2. Physical Design

3. Analog layout

4. Analog custom layout